ETH Zurich Education and Research SoCs

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Basilisk
Chiffre
Chiffre
Crocodilo
Crocodilo
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Fluffy
Hati
Hati
Koopa
Koopa
Mlem
Mlem
Pjononcroc
Pjononcroc
Skoll
Skoll
12nm RISC-V uLinux SoC Layout
12nm RISC-V uLinux SoC Layout

3D Layout Visualization using Blender

Visualizing the autonomous RTL-to-GDSII flow results -> Source: aesc-silicon/i2c-gpio-expander

OpenROAD Generated Layout - View 0
OpenROAD Generated Layout - View 0
OpenROAD Generated Layout - View 1
OpenROAD Generated Layout - View 1
OpenROAD Generated Layout - View 2
OpenROAD Generated Layout - View 2
OpenROAD Generated Layout - View 3
OpenROAD Generated Layout - View 3

OpenROAD Demo Designs

Routed layout visualizations from the OpenROAD demo regression suite -> Source: The-OpenROAD-Project/bazel-orfs

SERV – Bit-serial RISC-V CPU
SERV – Bit-serial RISC-V CPU
PicoRV32 – Size-optimized RISC-V CPU
PicoRV32 – Size-optimized RISC-V CPU
VLSIffra – 32-bit pipelined multiplier
VLSIffra – 32-bit pipelined multiplier
CoralNPU – RISC-V NPU core
CoralNPU – RISC-V NPU core
PyMTL3 – Stream checksum unit
PyMTL3 – Stream checksum unit
Gemmini – Systolic array accelerator
Gemmini – Systolic array accelerator
Gemmini 2×2 – Systolic array configuration
Gemmini 2×2 – Systolic array configuration
Gemmini 4×4 – Systolic array configuration
Gemmini 4×4 – Systolic array configuration
Gemmini 8×8 – Systolic array configuration
Gemmini 8×8 – Systolic array configuration
Gemmini 8×8 Abutted – Systolic array configuration
Gemmini 8×8 Abutted – Systolic array configuration