In the world of chip design, 2025 will be remembered as the year open-source EDA (Electronic Design Automation) truly hit its stride. At OpenROAD, our mission has always been to democratize silicon design, and this past year we took massive leaps toward making that a reality.

We spent the year strengthening the “bones” of our platform. By refining our timing closure, routing, and placement tools, we’ve made it easier than ever to achieve professional-grade Power, Performance, and Area (PPA) without the traditional barriers to entry.

Whether you are a researcher, a startup founder building an AI powerhouse, or a student, OpenROAD is evolving to meet your needs. We are proving that open, reproducible silicon design isn’t just a dream—it’s the new standard.

OpenROAD continues to foster innovation while helping scale education and workforce development efforts around the world. We’re seeing OpenROAD-based tools and flows, increasingly used by students and early-career engineers in courses, design contests, and chip shuttle programs.

We’re excited to report that OpenROAD is now governed by the OpenROAD Initiative (ORI), launched as part of an NSF POSE Phase II award since September 2025. ORI continues to operate under the leadership of UCSD, with active involvement from industry maintainers led by Precision Innovations and supported by Arizona State University and Brown University. Together, these partners are focused on growing, strengthening, and sustaining the OpenROAD EDA ecosystem. OpenROAD is also deployed within ChipsHub as part of the NSF award to enable scalable access to open-source chip design workflows and infrastructure for research, education, and early-stage innovation.

2025 Highlights at a Glance

In 2025, OpenROAD achieved important milestones in advancing its toolchain and flow towards deeper optimization, core infrastructure, architectural extensibility, and addressing emerging design and packaging challenges as follows:

Stronger Foundation for next-generation chip design
- 3DIC:Established a robust foundation by adding hierarchical physical design support and native 3DIC (3Dblox) data models for scalable optimization and advanced packaging workflows.
- AI & Research: OpenROAD is now a primary vehicle for developing next-gen AI accelerators and exploring the frontier of LLM-driven chip design e.g design copilot, flow assistants.
Improved Timing Closure
- Achieved improved timing closure through the introduction of resistance-aware, timing-driven global routing, integrated end-to-end clock NDRs. We added a new global routing, CUGR-2 that has improved layer assignment.
Improved QoR in Placement & CTS
- Significantly improved Quality of Results (QoR) by unifying and enhancing macro and pin placement with congestion- and hierarchy-aware optimization, delivering consistent CTS timing gains (4–7% average TNS, up to 36%+).
Better Usability & Productivity
- Added support for native SystemVerilog synthesis, improvements across key floorplanning and placement features–, rectilinear floorplanning, automated pad placement, and enhanced IR-drop analysis.

Read on for further details on each of these areas of progress.

Continuous Improvements:Infrastructure, PPA

Strengthened Core Infrastructure & Data Model

Introduced hierarchical physical design support in the OpenROAD database (ODB), enabling hierarchy-aware optimization and analysis across module boundaries.
Added new hierarchical objects that enable future capabilities such as:
- Hierarchy-aware buffering
- Port-level physical reasoning
- Cross-module optimization

3DIC Designs

OpenROAD extended its database (ODB) to natively support 3D heterogeneous integration (3DIC) designs aligned with the 3Dblox standard, including multi-chip assemblies, chiplets, and cross-die connectivity.

A 3Dblox linter was implemented to validate the structural and geometric correctness of 3DIC designs. It detects disconnected (floating) chiplets and identifies physical overlaps between chiplets, ensuring assembly-level correctness in multi-die designs.
Design and errors can be visualized in bump map viewer and linter error browser as shown below:

Smarter, Timing- and Resistance-Aware Routing

Integrated clock non-default routing rules (NDRs) through global routing, closing a long-standing resource-accounting and congestion gap.
Added resistance-aware, timing-driven global routing, enabling:
- Selective promotion of timing-critical nets to lower-resistance metal layers
- Improved timing closure in congested designs
Integrated CUGR-2 as an alternative 3D-grid-based global router, improving support for technologies with strict via constraints.

Placement, Macro Placement & Floorplanning

Macro Placement Enhancements

Retired TritonMacroPlacer and standardized on HierRTLMP as the sole macro placement engine in OpenROAD.
Improved overall robustness, maintainability, and consistency of the macro placement flow.

Flexible Placement Capabilities

Added support for partial automated placement, allowing users to pre-place selected macros while the tool places remaining macros.
Enabled correct handling of macros partially inside the core area and differentiation between macros inside and outside designated placement regions.

I/O and pad Awareness

Extended support to designs with placed and/or unplaced I/O pins using user-defined constraint regions.
Added proper I/O pad support, accounting for PAD connectivity to macros and standard cells during placement.

Improved Clustering and Optimization

Introduced hierarchy-aware virtual connections between macros and nearby standard cells to improve physical proximity.
Automated clustering criteria based on connection ratios, improving stability across designs with large size disparities.
Reduced downstream congestion using peripheral-bias–based simulated annealing instead of edge-distance heuristics.

Constraint and Robustness Enhancements

Modeled blockages as hard constraints, including both user-defined and tool-generated blockages.
Eliminated floating-point internal position handling, resolving long-standing bugs and unpredictable behavior.

Placement Quality Improvements

Enhanced the snapping engine to support multi-layer, multi-pattern pin alignment.
Improved notch detection and resolution to reduce unusable dead space and downstream congestion.

New Buffering Algorithm

New buffering algorithm during timing-driven placement that significantly improves metrics across PPA and placement density.
Added support for rectilinear (non-rectangular) floorplans, extending OpenROAD to more realistic die geometries. This was a GSoC 2025 project contribution.

Clock Tree Synthesis (CTS) Quality & Timing Gains

Enhanced clock-gater handling by identifying widely separated sink clusters and cloning clock gaters to drive each cluster, improving clock distribution in gated trees. Achieved ~4% average setup TNS improvement, with up to 90% improvement in select designs (e.g., ibex on sky130)
Improved skew minimization by extending latency adjustment across the entire clock tree, including clock-gating sub-trees. Delivered ~6% average setup TNS improvement in public PDK designs
Integrated clock net repair into CTS, addressing fanout, transition, and capacitance constraints within the clock_tree_synthesis flow. Resulted in ~6.5% setup TNS and ~8.6% setup WNS improvements on average
Refined sink clustering by separating macros from registers, enabling appropriate cluster sizing and more accurate wire delay modeling. Improved setup TNS by up to 16% in macro-heavy designs and ~7% on average across public PDKs
Enabled obstruction-aware CTS by default, improving robustness in congested layouts. Achieved equal or better timing QoR in ~90% of designs, with up to 36% setup TNS improvement in complex cases (e.g., asap7 / riscv32i. Delivered consistent timing improvements across public PDKs, with especially strong gains in congested and macro-intensive designs.

Usability, Productivity & Analysis

Enabled native SystemVerilog synthesis in the reference flow, eliminating fragile conversion steps and improving quality of results.
Added incremental pin access, enabling safe and correct design updates during and after global routing.
Introduced automated pad placement that positions pads along the die edge while minimizing RDL routing length and respecting fixed obstacles such as probe pads and chip markers.
Enhanced IR Drop Analysis: A new set of controls enables more flexible “what-if” IR drop analysis, allowing users to model input resistance and selectively control power to specific regions of the power grid for more granular power-integrity evaluation.

Overall Impact of Technology Enhancements

Advanced OpenROAD from feature completeness toward optimization depth and core infrastructure.
Established a stronger foundation for:
- Timing-driven physical design at scale
- Advanced packaging and 3DIC research
- Open, reproducible, production-relevant silicon workflows

OpenROAD Conferences and EWD Programs: Key Highlights

At DAC 2025, OpenROAD was a pivotal agent of ecosystem engagement at the Open-Source EDA & Open Data Birds-of-a-Feather (BoF) session, where the community highlighted reproducible RTL-to-GDSII flows, ML-ready design data, and OpenROAD’s growing role as shared infrastructure for research, education, and early product prototyping. ORConf 2025 (Europe) and Latch-Up 2025 reinforced developer–user engagement, with technical discussions around ORFS robustness, placement and routing QoR, timing closure, and integration with open PDK and verification ecosystems.

Education and workforce development expanded significantly through sustained OpenROAD deployment in academic programs. Multiple hands-on workshops and credited courses at IIT Guwahati trained students on full RTL→GDSII design using OpenROAD, Yosys, OpenSTA, and KLayout. These courses emphasized production-style constraints, signoff-aware flows, and tapeout-driven learning, aligning closely with national and international EDA workforce development (EWD) objectives.

The Semiconductor sector service bureau (S3BU) of Australia delivered a training course in digital design based on OpenROAD for undergraduate, graduate and industry professionals.

Other popular courses and workshops using OpenROAD include:

Courses and shuttles from TinyTapeout, IHP Design Lab:
- TinyTapeout:https://tinytapeout.com/guides/local-hardening/
- https://ihp-open-ip.readthedocs.io/en/latest/orfs.html
ETH Zurich - https://vlsi.ethz.ch/wiki/Main_Page

OpenROAD supported multiple fabrication pathways, including MPW shuttles at IHP (SG13G2), open shuttle programs operated by Wafer.Space, and commercial-adjacent community services such as ChipFoundry. In parallel, Tiny Tapeout completed multiple 2025 runs across SKY130- and IHP-based processes, enabling hundreds of student, researcher, and early-stage startup designs to reach fabrication using fully open flows. These shuttles are extremely popular in chip design education and serve as a main platform to deliver practical, hands-on education at scale. OpenROAD plays a vital role as a low-cost, accessible, production-relevant physical design backbone, bridging education, research, and workforce development.

OpenROAD and ORFS in LLM-Based Design Research

In 2025, OpenROAD and OpenROAD-Flow-Scripts (ORFS) became the reference execution platform for emerging LLM- and agent-based chip design research. Unlike prior exploratory studies, multiple peer-reviewed papers and open repositories used OpenROAD as a closed-loop backend, where AI systems directly ran full RTL-to-GDSII flows, observed quantitative outcomes (timing, congestion, wirelength), and iteratively improved results. This shift positioned OpenROAD not just as a design tool, but as a shared research infrastructure for AI-native EDA.

Research such as ORFS-agent (arXiv, 2025) demonstrated LLM-driven agents that automatically tuned OpenROAD flow parameters and measurably improved design quality over baseline heuristics. These studies relied on ORFS for repeatable experimentation and scale, validating OpenROAD as a practical environment for autonomous optimization rather than a proxy model.

OpenROAD-centric datasets and assistants accelerated LLM adoption in EDA. OpenROAD-Research and ORFS-Research were created as foundational platforms to accelerate collaboration, preserve algorithmic diversity and drive innovation in physical design. Public repositories such as and EDA-Corpus supported reproducible research, while systems like ORAssistant showed how retrieval-augmented LLMs could assist users in invoking, configuring, and debugging OpenROAD flows. OpenROAD will continue to advance the SOTA in LLM-based design.

Looking Ahead

OpenROAD continues to advance its mission to democratize chip design and accelerate innovation across research, industry, and education. In 2025, this mission was strengthened by the NSF award, enabling the growth, sustainability, and long-term stewardship of OpenROAD.

Conclusion

In 2025, OpenROAD strengthened its foundations while expanding its impact. Significant advances in core infrastructure, optimization, and quality of results position OpenROAD to meet the demands of next-generation designs, including hierarchical systems, 3DIC, and advanced packaging.

OpenROAD continues to be a strong catalyst for innovation in future chip design—enabling open, silicon-proven workflows across education, research, and emerging AI-driven methodologies. With long-term stewardship under the OpenROAD Initiative (ORI), OpenROAD is poised to continue shaping a more open, accessible, and innovative EDA ecosystem.